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Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation - Wehmeyer, Lars / Marwedel, Peter
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ISBN: 9789048172009

The memory system is increasingly turning into a bottleneck in the design of embedded systems. The speed improvements of memory systems are lower than the speed improvements of processors… Meer...

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Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation
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Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation - nieuw boek

ISBN: 9789048172009

The memory system is increasingly turning into a bottleneck in the design of embedded systems. The speed improvements of memory systems are lower than the speed improvements of processors… Meer...

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Fast, Efficient and Predictable Memory Accesses : Optimization Algorithms for Memory Architecture Aware Compilation - Peter Marwedel; Lars Wehmeyer
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Peter Marwedel; Lars Wehmeyer:
Fast, Efficient and Predictable Memory Accesses : Optimization Algorithms for Memory Architecture Aware Compilation - gebruikt boek

ISBN: 9048172004

Speed improvements in memory systems have not kept pace with the speed improvements of processors, leading to embedded systems whose performance is limited by the memory. This book presen… Meer...

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Fast Efficient and Predictable Memory Accesses - pocketboek

2006, ISBN: 9048172004

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Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation

Speed improvements in memory systems have not kept pace with the speed improvements of processors, leading to embedded systems whose performance is limited by the memory. This book presents design techniques for fast, energy-efficient and timing-predictable memory systems that achieve high performance and low energy consumption. In addition, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds.

Gedetalleerde informatie over het boek. - Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation


EAN (ISBN-13): 9789048172009
ISBN (ISBN-10): 9048172004
Gebonden uitgave
pocket book
Verschijningsjaar: 2010
Uitgever: Springer-Verlag GmbH
272 Bladzijden
Gewicht: 0,438 kg
Taal: eng/Englisch

Boek bevindt zich in het datenbestand sinds 2011-07-10T19:28:42+02:00 (Amsterdam)
Detailpagina laatst gewijzigd op 2021-08-08T20:57:18+02:00 (Amsterdam)
ISBN/EAN: 9789048172009

ISBN - alternatieve schrijfwijzen:
90-481-7200-4, 978-90-481-7200-9


Gegevens van de uitgever

Auteur: Lars Wehmeyer; Peter Marwedel
Titel: Fast, Efficient and Predictable Memory Accesses - Optimization Algorithms for Memory Architecture Aware Compilation
Uitgeverij: Springer; Springer Netherland
258 Bladzijden
Verschijningsjaar: 2010-10-19
Dordrecht; NL
Gedrukt / Gemaakt in
Gewicht: 0,440 kg
Taal: Engels
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
POD

BC; Previously published in hardcover; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Compiler; DRAM; Energy; Memory; RAM; Timing Predictability; embedded systems; processor; B; Circuits and Systems; Computer System Implementation; Operating Systems; Processor Architectures; Optical and Electronic Materials; Electronics and Microelectronics, Instrumentation; Electronic Circuits and Systems; Computer System Implementation; Operating Systems; Processor Architectures; Optical Materials; Electronics and Microelectronics, Instrumentation; Engineering; Systemanalyse und -design; Betriebssysteme; Rechnerarchitektur und Logik-Entwurf; Elektronische Geräte und Materialien; Elektronik; BB

1 Abstract. 2 Introduction. 2.1 Motivation. 2.2 Contributions of this Work. 2.3 Overview. 3 Models and Tools. 3.1 Instruction Set Architecture Model. 3.2 Memory Models. 3.3 Timing Models. 3.4 Energy Models.3.5 Simulation Models. 3.6 The encc Compiler Framework. 4 Scratchpad Memory Optimizations. 4.1 Related Work. 4.2 Multi Memory Optimization. 4.3 Impact of Scratchpad Allocation Techniques on WCET. 5 Main Memory Optimizations. 5.1 Related Work. 5.2 Main Memory Power Management. 5.3 Execute-In-Place using Flash Memories. 6 Register File Optimization. 6.1 Related Work. 6.2 Implementation of the Register File. 6.3 Register Allocation and Lifetime Analysis. 6.4 Workflow and Methodology. 6.5 Benchmark Suite. 6.6 Compiler Guided Choice of Register File Size. 7 Summary. 8 Future Work. Index. References.

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