CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test - nieuw boek
2010, ISBN: 9789048178551
Kartoniert, 212 Seiten, 235mm x 155mm x 12mm, Sprache(n): eng Gives a process-aware perspective on SRAM circuit design and test Provides detailed coverage of SRAM cell stability, stabilit… Meer...
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2008, ISBN: 9789048178551
*CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies* - Process-Aware SRAM Design and Test. Softcover reprint of hardcover 1st ed. 2008 / Taschenbuch für 160.49 € / A… Meer...
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test - pocketboek
2010, ISBN: 904817855X
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Softcover reprint of hardcover 1st ed. 2008 Kartoniert / Broschiert Computerhardware, Transistor; integrated circuit; static-induction transistor; DOM; RAM, mit Schutzumschlag 11, [PU:S… Meer...
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test - pocketboek
2010, ISBN: 904817855X
gebonden uitgave
Softcover reprint of hardcover 1st ed. 2008 Kartoniert / Broschiert Computerhardware, DOM; RAM; Transistor; integratedcircuit; static-inductiontransistor, mit Schutzumschlag 11, [PU:Spr… Meer...
Achtung-Buecher.de MARZIES.de Buch- und Medienhandel, 14621 Schönwalde-Glien Verzendingskosten:Versandkostenfrei innerhalb der BRD. (EUR 0.00) Details... |
ISBN: 9789048178551
Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data … Meer...
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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test - nieuw boek
2010, ISBN: 9789048178551
Kartoniert, 212 Seiten, 235mm x 155mm x 12mm, Sprache(n): eng Gives a process-aware perspective on SRAM circuit design and test Provides detailed coverage of SRAM cell stability, stabilit… Meer...
Andrei Pavlov/ Manoj Sachdev:
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies - pocketboek2008, ISBN: 9789048178551
*CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies* - Process-Aware SRAM Design and Test. Softcover reprint of hardcover 1st ed. 2008 / Taschenbuch für 160.49 € / A… Meer...
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test - pocketboek
2010
ISBN: 904817855X
gebonden uitgave
Softcover reprint of hardcover 1st ed. 2008 Kartoniert / Broschiert Computerhardware, Transistor; integrated circuit; static-induction transistor; DOM; RAM, mit Schutzumschlag 11, [PU:S… Meer...
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test - pocketboek
2010, ISBN: 904817855X
gebonden uitgave
Softcover reprint of hardcover 1st ed. 2008 Kartoniert / Broschiert Computerhardware, DOM; RAM; Transistor; integratedcircuit; static-inductiontransistor, mit Schutzumschlag 11, [PU:Spr… Meer...
ISBN: 9789048178551
Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data … Meer...
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Gedetalleerde informatie over het boek. - CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
EAN (ISBN-13): 9789048178551
ISBN (ISBN-10): 904817855X
Gebonden uitgave
pocket book
Verschijningsjaar: 2010
Uitgever: Springer Netherlands
212 Bladzijden
Gewicht: 0,328 kg
Taal: eng/Englisch
Boek bevindt zich in het datenbestand sinds 2011-05-06T21:52:55+02:00 (Amsterdam)
Detailpagina laatst gewijzigd op 2024-02-22T00:02:19+01:00 (Amsterdam)
ISBN/EAN: 9789048178551
ISBN - alternatieve schrijfwijzen:
90-481-7855-X, 978-90-481-7855-1
alternatieve schrijfwijzen en verwante zoekwoorden:
Auteur van het boek: pavlov
Titel van het boek: cmos design, nano, cmos technologie, best test design, around the circuit, sram, process design
Gegevens van de uitgever
Auteur: Andrei Pavlov; Manoj Sachdev
Titel: Frontiers in Electronic Testing; CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies - Process-Aware SRAM Design and Test
Uitgeverij: Springer; Springer Netherland
194 Bladzijden
Verschijningsjaar: 2010-10-28
Dordrecht; NL
Gedrukt / Gemaakt in
Gewicht: 0,454 kg
Taal: Engels
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
POD
XVI, 194 p.
BC; Circuits and Systems; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; CMOS; DOM; RAM; SRAM; Transistor; integrated circuit; static-induction transistor; Memory Structures; Electronic Circuits and Systems; Computer Memory Structure; Computerhardware; BB
Foreword. Preface. Acronyms. 1. INTRODUCTION AND MOTIVATION. 1.1 Motivation. 1.2 SRAM in the Computer Memory Hierarchy. 1.3 Technology Scaling and SRAM Design and Test. 1.4 SRAM test economics. 1.5 SRAM Design and Test Tradeoffs. 1.6 Redundancy. 2. SRAM CIRCUIT DESIGN AND OPERATION. 2.1 Introduction. 2.2 SRAM block structure. 2.3 SRAM cell design. 2.4 Cell layout considerations. 2.5 Sense Amplifier and Bit Line Precharge-Equalization. 2.6 Write Driver. 2.7 Row Address Decoder and Column MUX. 2.8 Address Transition Detector. 2.9 Timing Control Schemes. 2.10 Summary. 3. SRAM CELL STABILITY: DEFINITION, MODELING AND TESTING. 3.1 Introduction. 3.2 Static noise margin of SRAM cells. 3.3 SNM Definitions. 3.4 Analytical expressions for SNM calculations. 3.5 SRAM cell stability sensitivity factors. 3.6 SRAM cell stability fault model. 3.7 SRAM Cell Stability Detection Concept. 3.8 March tests and stability fault detection in SRAMs. 3.9 Summary. 4. TRADITIONAL SRAM FAULT MODELS AND TEST PRACTICES. 4.1 Introduction. 4.2 Traditional fault models. 4.3 Traditional SRAM test practices. 4.4 Summary. 5. TECHNIQUES FOR DETECTION OF SRAM CELLS WITH STABILITY FAULTS. 5.1 Introduction. 5.2 Classification of SRAM cell stability test techniques. 5.3 Passive SRAM Cell Stability Test Techniques. 5.4 Active SRAM Cell Stability Test Techniques. 5.5 Summary. 6. SOFT ERROR IN SRAMs: SOURCES, MECHANISM AND MITIGATION TECHNIQUES. 6.1 Introduction. 6.2 Soft Error Mechanism. 6.3 Sources of Soft Errors. 6.4 Soft Errors and Defects in the Pull-Up Path of a Cell. 6.5 Soft Error Mitigation Techniques. 6.6 Leakage-Reduction Techniques and the SER. 6.7 Summary. References. Index.Andere boeken die eventueel grote overeenkomsten met dit boek kunnen hebben:
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