ISBN: 9789048178858

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed a… Meer...

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size. Trade Books>Trade Paperback>Science>Engineering>ELEC Engr, Springer Netherlands Core >1<

2010, ISBN: 9789048178858

gebonden uitgave

[ED: Taschenbuch], [PU: Springer Netherland], Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achie… Meer...

[ED: Taschenbuch], [PU: Springer Netherland], Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can..., DE, [SC: 0.00], Neuware, gewerbliches Angebot, 112, [GW: 184g], Softcover reprint of hardcover 1st ed. 2008, Banküberweisung, PayPal, [CT: Sonstiges / Sonstiges]<

2010, ISBN: 9789048178858

pocketboek, gebonden uitgave

gewerbliches Angebot, [SC: 0.00], Neuware, [PU: Springer Netherland], 112, [GW: 184g], [ED: Taschenbuch], Softcover reprint of hardcover 1st edition 2008, DE, Low-Power High-Speed ADCs fo… Meer...

gewerbliches Angebot, [SC: 0.00], Neuware, [PU: Springer Netherland], 112, [GW: 184g], [ED: Taschenbuch], Softcover reprint of hardcover 1st edition 2008, DE, Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can..., Banküberweisung, PayPal, [CT: Sonstiges / Sonstiges]<

2010, ISBN: 9789048178858

pocketboek, gebonden uitgave

gewerbliches Angebot, [SC: 0.00], Neuware, [PU: Springer], 112, [GW: 184g], [ED: Taschenbuch], Softcover reprint of hardcover 1st edition 2008, DE, Low-Power High-Speed ADCs for Nanometer… Meer...

gewerbliches Angebot, [SC: 0.00], Neuware, [PU: Springer], 112, [GW: 184g], [ED: Taschenbuch], Softcover reprint of hardcover 1st edition 2008, DE, Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can..., Banküberweisung, PayPal, [CT: Sonstiges / Sonstiges]<

2010, ISBN: 9789048178858

Mitwirkende: Yan, Shouli, Springer, Taschenbuch, Auflage: Softcover reprint of hardcover 1st ed. 2008, 112 Seiten, Publiziert: 2010-11-22T00:00:01Z, Produktgruppe: Buch, 0.37 kg, Industri… Meer...

Mitwirkende: Yan, Shouli, Springer, Taschenbuch, Auflage: Softcover reprint of hardcover 1st ed. 2008, 112 Seiten, Publiziert: 2010-11-22T00:00:01Z, Produktgruppe: Buch, 0.37 kg, Industrie, Branchen & Berufe, Business & Karriere, Kategorien, Bücher, Umweltwissenschaft, Naturwissenschaft & Mathematik, Fachbücher, Schaltkreise, Elektrotechnik, Ingenieurwissenschaft & Technik, Naturwissenschaften & Technik, Elektronik, Energietechnik, Energiefragen, Umwelt & Ökologie, Verschiedenes, Englische Bücher, 7c9a6c79-19ea-4dea-90da-d7d47042d341_2301, 7c9a6c79-19ea-4dea-90da-d7d47042d341_0, Arborist Merchandising Root, Fremdsprachige Bücher, acc906d0-2585-4921-a56f-3ff277850936_4901, acc906d0-2585-4921-a56f-3ff277850936_0, Special Features Stores, Taschenbücher, acc906d0-2585-4921-a56f-3ff277850936_4201, Springer, 2010<