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[EAN: 9789048181001], Neubuch, [SC: 0.0], [PU: Springer Netherlands], C-BASE; DESIGNSPACEEXPLORATION; ELECTRONICSYSTEMLEVELDESIGN; EMBEDDEDSYSTEM; RE-CONFIGURABLEPROCESSOR; ROUTING; SEGME… Meer...
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2010, ISBN: 9789048181001
Mitwirkende: Leupers, Rainer, Mitwirkende: Meyr, Heinrich, Mitwirkende: Ascheid, Gerd, Springer, Taschenbuch, Auflage: Softcover reprint of hardcover 1st ed. 2009, 216 Seiten, Publiziert:… Meer...
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2010, ISBN: 9789048181001
Mitwirkende: Leupers, Rainer, Mitwirkende: Meyr, Heinrich, Mitwirkende: Ascheid, Gerd, Springer, Taschenbuch, Auflage: Softcover reprint of hardcover 1st ed. 2009, 216 Seiten, Publiziert:… Meer...
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2010, ISBN: 9789048181001
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ISBN: 9789048181001
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2010, ISBN: 9048181003
[EAN: 9789048181001], Neubuch, [SC: 0.0], [PU: Springer Netherlands], C-BASE; DESIGNSPACEEXPLORATION; ELECTRONICSYSTEMLEVELDESIGN; EMBEDDEDSYSTEM; RE-CONFIGURABLEPROCESSOR; ROUTING; SEGME… Meer...

Chattopadhyay, Anupam:
Language-driven Exploration and Implementation of Partially Re-configurable ASIPs - pocketboek2010, ISBN: 9789048181001
Mitwirkende: Leupers, Rainer, Mitwirkende: Meyr, Heinrich, Mitwirkende: Ascheid, Gerd, Springer, Taschenbuch, Auflage: Softcover reprint of hardcover 1st ed. 2009, 216 Seiten, Publiziert:… Meer...

2010
ISBN: 9789048181001
Mitwirkende: Leupers, Rainer, Mitwirkende: Meyr, Heinrich, Mitwirkende: Ascheid, Gerd, Springer, Taschenbuch, Auflage: Softcover reprint of hardcover 1st ed. 2009, 216 Seiten, Publiziert:… Meer...

2010, ISBN: 9789048181001
pocketboek
[ED: Kartoniert / Broschiert], [PU: Springer Netherlands], Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. This book presents a strong bac… Meer...

ISBN: 9789048181001
Paperback, [PU: Springer], Increasing complexity of modern embedded systems demands system designers to ramp up their design productivity without compromising performance goals., Circuits… Meer...
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Gedetalleerde informatie over het boek. - Language-driven Exploration and Implementation of Partially Re-configurable ASIPs
EAN (ISBN-13): 9789048181001
ISBN (ISBN-10): 9048181003
Gebonden uitgave
pocket book
Verschijningsjaar: 2010
Uitgever: Springer
216 Bladzijden
Gewicht: 0,334 kg
Taal: eng/Englisch
Boek bevindt zich in het datenbestand sinds 2011-07-10T04:44:20+02:00 (Amsterdam)
Detailpagina laatst gewijzigd op 2023-01-09T23:27:03+01:00 (Amsterdam)
ISBN/EAN: 9789048181001
ISBN - alternatieve schrijfwijzen:
90-481-8100-3, 978-90-481-8100-1
alternatieve schrijfwijzen en verwante zoekwoorden:
Auteur van het boek: gerd heinrich, chatto, rainer, meyr, chattopadhyay
Titel van het boek: language
Gegevens van de uitgever
Auteur: Anupam Chattopadhyay; Rainer Leupers; Heinrich Meyr; Gerd Ascheid
Titel: Language-driven Exploration and Implementation of Partially Re-configurable ASIPs
Uitgeverij: Springer; Springer Netherland
203 Bladzijden
Verschijningsjaar: 2010-10-19
Dordrecht; NL
Gedrukt / Gemaakt in
Gewicht: 0,454 kg
Taal: Engels
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
POD
IX, 203 p.
BC; Circuits and Systems; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; C-base; Design Space Exploration; Electronic System Level Design; Embedded System; Re-configurable Processor; Routing; Segment; Computer Communication Networks; Special Purpose and Application-Based Systems; Electronic Circuits and Systems; Computer Communication Networks; Special Purpose and Application-Based Systems; Netzwerk-Hardware; Wissensbasierte Systeme, Expertensysteme
1 Introduction. 2 Background. 2.1 Processor Design: A Retrospection. 2.2 High-level Processor Modelling. 2.3 Library-based Processor Design. 2.4 Partially Re-configurable Processors: A Design Alternative. 2.5 Synopsis. 3 Related Work. 3.1 A Chronological Overview of the Expanding rASIP Design Space. 3.2 rASIP Design: High-level Modelling Approach. 3.3 rASIP Design: Library-based Approach. 3.4 Independent rASIP Design Tools. 3.5 Motivation. 3.6 Synopsis. 4 rASIP Design Space. 4.1 Architecture Design Points. 4.2 Language-based rASIP Modelling. 4.3 Language-based rASIP Design Flow. 4.4 Synopsis. 5 Pre-fabrication Design Space Exploration. 5.1 Pre-fabrication Design Decisions. 5.2 Application Characterization. 5.3 Software Tool-suite Generation for rASIP. 5.4 Partitioning the ISA: Coding Leakage Exploration. 5.5 Synopsis. 6 Pre-fabrication Design Implementation. 6.1 Base Processor Implementation. 6.2 Partitioning the Structure: Specification Aspects. 6.3 Partitioning the Structure: Implementation Aspects. 6.4 Latency: Multiple Clock Domain Implementation. 6.5 Automatic Interface Generation and Storage. 6.6 Background for FPGA Implementation. 6.7 FPGA Implementation: RTL Synthesis. 6.8 Background for Synthesis on FPGA. 6.9 FPGA Synthesis: Mapping and Clustering. 6.10 FPGA Synthesis: Placement and Routing. 6.11 Synopsis. 7 Post-fabrication Design Space Exploration and Implementation. 7.1 Post-fabrication Design Space Exploration. 7.2 Post-fabrication Design Implementation. 7.3 Synopsis. 8 Case Study. 8.1 Introduction. 8.2 Experiments with RISC-based Architecture. 8.3 Experiments with VLIW-based Architecture. 8.4 Experiments with Coarse-grained FPGA Exploration. 8.5 rASIP Modelling for W-CDMA. 9 Past, Present and Future. 9.1 Past. 9.2 Present. 9.3 Future.Andere boeken die eventueel grote overeenkomsten met dit boek kunnen hebben:
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