Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs Pedro M. Figueiredo Author - nieuw boek

EAN (ISBN-13): 9789048181926
ISBN (ISBN-10): 9048181925
Gebonden uitgave
pocket book
Verschijningsjaar: 2010
Uitgever: Springer Netherlands Core >1 >T
404 Bladzijden
Gewicht: 0,608 kg
Taal: eng/Englisch

Boek bevindt zich in het datenbestand sinds 2011-04-13T02:12:22+02:00 (Amsterdam)
Detailpagina laatst gewijzigd op 2024-02-13T14:38:27+01:00 (Amsterdam)
ISBN/EAN: 9789048181926

ISBN - alternatieve schrijfwijzen:
90-481-8192-5, 978-90-481-8192-6
alternatieve schrijfwijzen en verwante zoekwoorden:
Auteur van het boek: not vital, figu, figueiredo pedro vital
Titel van het boek: speed what you need, vital, ever more speed, high speed digital design, converter set, converters techniques reduction digital analog offset speed high

---

Gegevens van de uitgever

Auteur: Pedro M. Figueiredo; João C. Vital
Titel: Analog Circuits and Signal Processing; Offset Reduction Techniques in High-Speed Analog-to-Digital Converters - Analysis, Design and Tradeoffs
Uitgeverij: Springer; Springer Netherland
382 Bladzijden
Verschijningsjaar: 2010-10-28
Dordrecht; NL
Gedrukt / Gemaakt in
Taal: Engels
192,59 € (DE)
197,99 € (AT)
212,50 CHF (CH)
POD
XX, 382 p.

BC; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Analog-to-Digital Converter; Averaging; CMOS; Kickback noise; Offset Calibration; design automation; Electronic Circuits and Systems; Input/Output and Data Communications; Computerhardware; BB; EA

Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed. Since the offset voltages of the constituting sub-blocks of these converters (pre-amplifiers, folding circuits and latched comparators) present the definitive linearity limitation, the offset is the fundamental design parameter in high-speed CMOS ADCs. Consequently, offset reduction techniques must be employed, in order to achieve high frequency operation with low power and layout area. Averaging and offset sampling are the most widely used, both being thoroughly characterized: the most exhaustive study ever performed about averaging in both pre-amplifier and folding stages is presented, covering the DC and transient responses, all mismatch sources, termination, and a fully automated design procedure; existing offset sampling methods are carefully reviewed, and two new techniques are disclosed that, combined, yield a (nearly) offset free comparator. Other relevant topics include kickback noise elimination in comparators, reference buffer design, a technique to compensate (certain) IR drops, details on the layout and floorplan of cascaded folding stages, and an improved scheme to select reference voltages in fine ADCs of two-step subranging converters. Special emphasis is given to the methods of guaranteeing specifications across process, temperature and supply voltage corners.
All high-speed ADC architectures (flash, two-step, folding and interpolation) covered in detail The performance parameters and trade-offs encountered in each of the ADC’s sub-blocks are analysed Most exhaustive study ever performed about averaging is presented Offset sampling techniques that yield a nearly offset free, high-speed, comparator are described