2010, ISBN: 9789048182008
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2010, ISBN: 904818200X
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2010, ISBN: 9789048182008
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2010, ISBN: 9789048182008
[ED: Softcover], [PU: Springer Netherlands], Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum… Meer...
ISBN: 9789048182008
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. Wi… Meer...
ISBN: 9789048182008
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. Wi… Meer...
2010, ISBN: 904818200X
gebonden uitgave
Softcover reprint of hardcover 1st ed. 2009 Kartoniert / Broschiert Elektrotechnik, Rechnerarchitektur und Logik-Entwurf, Design; NetworksonChips; reliability; SystemsonChips; Topology;… Meer...
2010, ISBN: 9789048182008
Buch, Softcover, Softcover reprint of hardcover 1st ed. 2009, [PU: Springer], Springer, 2010
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Gedetalleerde informatie over het boek. - Designing Reliable and Efficient Networks on Chips
EAN (ISBN-13): 9789048182008
ISBN (ISBN-10): 904818200X
Gebonden uitgave
pocket book
Verschijningsjaar: 2010
Uitgever: Springer
208 Bladzijden
Gewicht: 0,322 kg
Taal: eng/Englisch
Boek bevindt zich in het datenbestand sinds 2011-12-31T09:46:13+01:00 (Amsterdam)
Detailpagina laatst gewijzigd op 2024-03-19T02:16:45+01:00 (Amsterdam)
ISBN/EAN: 9789048182008
ISBN - alternatieve schrijfwijzen:
90-481-8200-X, 978-90-481-8200-8
alternatieve schrijfwijzen en verwante zoekwoorden:
Auteur van het boek: srinivasan
Titel van het boek: designing, chips
Gegevens van de uitgever
Auteur: Srinivasan Murali
Titel: Lecture Notes in Electrical Engineering; Designing Reliable and Efficient Networks on Chips
Uitgeverij: Springer; Springer Netherland
198 Bladzijden
Verschijningsjaar: 2010-10-28
Dordrecht; NL
Gedrukt / Gemaakt in
Taal: Engels
160,49 € (DE)
164,99 € (AT)
177,00 CHF (CH)
POD
X, 198 p.
BC; Hardcover, Softcover / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; Design; Networks on Chips; Reliability; Systems on Chips; Topology; integrated circuit; metal-oxide-semiconductor transistor; Electronic Circuits and Systems; Electrical Power Engineering; Processor Architectures; Elektrotechnik; Rechnerarchitektur und Logik-Entwurf; BB; EA
NoC Design Methods.- Designing Crossbar Based Systems.- Netchip Tool Flow for NoC Design.- Designing Standard Topologies.- Designing Custom Topologies.- Supporting Multiple Applications.- Supporting Dynamic Application Patterns.- NoC Reliability Mechanisms.- Timing-Error Tolerant NoC Design.- Analysis of NoC Error Recovery Schemes.- Fault-Tolerant Route Generation.- NoC Support for Reliable On-Chip Memories.- Conclusions and Future Directions.First book that presents in depth the state-of-the-art algorithms and optimization models for performing system-level design of NoCs Presents an integrated flow to design interconnect architectures that can lead to faster time-to-market and design closure Shows evolution of design methods from complex crossbar based buses to NoCs Presents static and run-time methods for achieving reliable operation of the NoC and the entire system Includes supplementary material: sn.pub/extras
Andere boeken die eventueel grote overeenkomsten met dit boek kunnen hebben:
Laatste soortgelijke boek:
9781402097560 Designing Reliable and Efficient Networks on Chips (Murali, Srinivasan)
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