2010, ISBN: 9789048182008

[ED: Softcover], [PU: Springer Netherlands], Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum… Meer...

[ED: Softcover], [PU: Springer Netherlands], Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design. 2010. X, 198 S. 235 mm Versandfertig in 3-5 Tagen, DE, [SC: 0.00], Neuware, gewerbliches Angebot, offene Rechnung (Vorkasse vorbehalten)<

ISBN: 9789048182008

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. Wi… Meer...

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design. Books > Computers > Advanced Computing > Engineering > Computer Architecture List_Books<

ISBN: 9789048182008

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. Wi… Meer...

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design. Books > Science & Nature > Science > Technology > Electronics List_Books<

2010, ISBN: 904818200X

gebonden uitgave

Softcover reprint of hardcover 1st ed. 2009 Kartoniert / Broschiert Elektrotechnik, Rechnerarchitektur und Logik-Entwurf, Design; NetworksonChips; reliability; SystemsonChips; Topology;… Meer...

Softcover reprint of hardcover 1st ed. 2009 Kartoniert / Broschiert Elektrotechnik, Rechnerarchitektur und Logik-Entwurf, Design; NetworksonChips; reliability; SystemsonChips; Topology; integratedcircuit; metal-oxide-semiconductortransistor, mit Schutzumschlag 11, [PU:Springer Netherlands; Springer Netherland]<

2010, ISBN: 9789048182008

Buch, Softcover, Softcover reprint of hardcover 1st ed. 2009, [PU: Springer], Springer, 2010